About Netpreme

The biggest bottleneck in AI systems today is memory. Chips compute faster than they can be fed data—a problem known as the memory wall—and Netpreme is building the solution that allows AI memory to scale independently of AI compute. Our approach spans the full stack, from a proprietary memory management framework at the XPU kernel and OS levels to X-Mem™, the world’s first Memory Processing Unit (MPU) silicon. Founded by MIT researchers at the intersection of optical networking, ML systems, and GPU kernel optimization, we’re based in Cambridge, MA, and Santa Clara, CA. We’re looking for people who want to own hard problems end to end—and help shape the next generation of AI systems.

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About the Role

We are seeking a Director of ASIC Verification who leads from the front: you'll own verification strategy, sign-off, and the team — and you'll also be one of the strongest hands-on verification engineers here, writing testbenches, closing coverage, and debugging the hardest failures.

This role will be performed onsite from our office in Santa Clara, CA.

The Opportunity

Impact: AI is advancing faster than the infrastructure underneath it. We’re working at that layer, unlocking more capability from every GPU while dramatically improving efficiency. The work you do here compounds across state-of-the-art models, systems, and real-world applications.

Timing: Joining now means real ownership, including equity, and a direct say in product direction. You’ll work from first principles, move quickly from insight to execution, and see your work show up in what we ship, not just in a roadmap.

Culture: We care about rigor, clarity, and impact. Disagreement is welcome when it’s thoughtful, the best idea wins regardless of who it comes from, and you’ll learn something new most weeks.

Your Impact

Own verification end-to-end: strategy, methodology (UVM, formal, emulation, coverage-driven closure), tape-out sign-off for Netpreme silicon, IP, subsystems and post silicon bringup support including test-vector generation.

Architect and author verification environments and testplans, review testbench code line-by-line, and personally drive debug of the hardest protocol, coverage, and bring-up issues

Recruit, lead, and develop a world-class verification organization that treats technical depth as the currency

Present verification readiness, metrics, and risk posture to engineering

leadership with conviction

Qualifications

BS/MS in Electrical Engineering, Computer Engineering, or related field.

8+ years of progressive ASIC/SOC verification, with 5+ years leading verification teams

Demonstrable experience writing verification code, building testbenches, and closing coverage

Multiple tapeouts in advanced process nodes where you owned both deep technical work and sign-off

Hands-on experience with high-speed protocol IP — Ethernet, UCIe, UALink, or comparable

Fluent across the full ASIC/SOC lifecycle — microarchitecture through tape-out — on designs integrating interconnect, I/O, and memory subsystems

Executive communication skills; proven ability to manage risk, escalations, budget, and headcount on startup timelines

Nice to Have

PhD in EE, CE, or related field

Built a verification team from zero at an early-stage startup while delivering milestones personally

Hands-on post-silicon bring-up, debug, and validation leadership

AI/datacenter accelerator background; familiarity with LLM memory/dataloader bottlenecks

Knowledge of DFT and its interaction with front-end verification

What We Offer

Competitive salary with performance-based bonus and early-stage equity grant

100% employer-paid Health, Dental, and Vision coverage for you and your dependents

401(k) match with immediate vesting, and access to financial advisors to help you reach your financial goals

100% employer-paid Life, Disability, and AD&D insurance, plus a fitness stipend and wellness & mental health perks

Generous PTO: 20 vacation days, 15 company holidays (including 3 floating days of your choosing)