Netradyne harnesses the power of Computer Vision and Edge Computing to revolutionize the modern-day transportation ecosystem. We are a leader in fleet safety solutions. With growth exceeding 4x year over year, our solution is quickly being recognized as a significant disruptive technology. Our team is growing, and we need forward-thinking, uncompromising, competitive team members to continue to facilitate our growth.

Job role : Staff/Senior Staff PCB Layout Design Engineer

Experience : 8+ to 15 Years

Location : Bengaluru (5days work from office)

About Netradyne

Netradyne provides AI-powered technologies for fleet management and safer roads. An award-winning industry leader in fleet safety and video telematics solutions, Netradyne empowers commercial fleet customers across North America, Europe, and Asia to enhance driver performance, reduce risk, and optimize operations.

Founded in 2015, Netradyne is headquartered in San Diego with offices in San Francisco, Nashville, the UK, and Bangalore. For more details, visit www.netradyne.com.

Job Overview

The Staff PCB Layout Design Engineer will lead the design and delivery of complex, high-density multilayer PCB layouts for embedded computing, vision, connectivity, and power applications. The role requires strong hands-on expertise in Cadence Allegro, high-speed and mixed-signal layout, HDI technologies, stack-up planning, signal and power integrity implementation, and design for manufacturing. The engineer will work closely with Hardware, SI/PI, RF, Mechanical, PCB fabrication, assembly, and manufacturing teams from design study through production release.

Key Responsibilities

Lead PCB layout activities from schematic study, floor planning, and critical component placement through routing, design verification, and manufacturing release.
Design complex multilayer PCBs for digital, analog, mixed-signal, RF, and power circuits using Cadence Allegro PCB Designer.
Develop placement and routing strategies for high-speed interfaces such as DDR, PCIe, USB, Ethernet, MIPI CSI/DSI, SDIO, eMMC/UFS, CAN, SPI, I2C, UART, and similar buses.
Plan BGA escape routing and HDI structures using microvias, blind/buried vias, through vias, via-in-pad, and back-drilling where required.
Define and implement constraint-driven design rules, electrical constraints, differential pairs, length-matching groups, clearance rules, and layer assignments in Allegro Constraint Manager.
Coordinate with PCB fabrication vendors to finalize stack-up, controlled-impedance geometry, materials, copper distribution, drill structures, and manufacturability requirements.
Implement SI, PI, EMI/EMC, return-path, grounding, power-plane, decoupling, and thermal recommendations provided by domain teams.
Perform layout self-reviews, DRC checks, DFM/DFA checks, Gerber/ODB++ reviews, and release-package verification.
Generate fabrication drawings, assembly drawings, artwork data, drill data, IPC-356 netlist, pick-and-place data, 3D/STEP outputs, and other manufacturing documentation.
Create, review, and maintain PCB component footprints, land patterns, padstacks, and library symbols based on manufacturer datasheets and applicable IPC standards, including IPC-7351 requirements; verify dimensions, courtyard, assembly, silkscreen, solder-mask, paste-mask, pin-1, polarity, and 3D model information before release.
Participate in cross-functional design reviews with Hardware, Mechanical, SI/PI, RF, Component Engineering, Manufacturing, and Quality teams.
Support prototype build, board bring-up, failure analysis, ECO implementation, and production issues related to PCB design.
Mentor PCB layout engineers, review critical designs, improve checklists and workflows, and drive PCB design automation and standardization.

Mandatory Skills and Qualifications

Bachelor's degree or diploma in Electronics, Electrical Engineering, with 8+ years of relevant PCB layout design experience.
Advanced hands-on expertise in Cadence Allegro PCB Designer and Constraint Manager.
Hands-on experience creating and validating PCB footprints and padstacks in accordance with IPC-7351 and company library standards, with strong understanding of component tolerances, manufacturing allowance, solder-joint goals, and datasheet interpretation.