Principal Semiconductor Device Engineer

Company Description

Vertical Semiconductor, a venture-backed MIT spin-out, is leading the development of vertical gallium nitride (GaN) power electronics to build the foundational power layer for the next generation of compute and AI.

Role Description

Vertical Semiconductor is seeking a Principal Semiconductor Device Engineer to serve as a senior technical contributor in the development and commercialization of our vertical GaN power device technology. This is a hands-on role is intended for an engineer with around 10-20 years of semiconductor R&D experience who can operate at the intersection of device physics, process integration, and manufacturability.

In this role, you will provide deep technical leadership across device architecture, process development, modeling, and characterization, while working closely with cross-functional partners in epitaxy, process engineering, packaging, reliability, and systems. You will play a critical role in defining device roadmaps, de-risking technology transitions, and guiding decisions that directly impact product performance and scalability.

This position offers the opportunity to help shape a world-changing power electronics platform at a pivotal stage, with direct influence on the company’s technical direction and long-term success. We prefer candidates who can work from our office at Greentown Labs (Somerville, MA).

Key Responsibilities

Serve as a technical subject-matter expert for vertical GaN and wide-bandgap power devices across the full R&D lifecycle, from concept through early production readiness

Lead the definition and evolution of device architectures, performance targets, and design trade-offs for next-generation vertical GaN power devices

Drive device modeling, simulation, and analytical understanding to guide design optimization, scaling strategies, and reliability improvements

Plan and execute device development programs in shared fabs and external foundries, including technology transfer and process co-development

Partner closely with internal and external teams on CMOS-compatible GaN process integration, yield learning, and manufacturability

Provide technical leadership in failure analysis, reliability physics, and root-cause investigations for wide-bandgap power devices

Oversee and interpret on-wafer and discrete device characterization, including DC, CV, dynamic, and high-power testing

Develop and review GDS layouts, test structures, and evaluation vehicles to support device learning and validation

Support system-level understanding through application evaluation boards, measurements, and correlation to device behavior

Mentor junior engineers and influence technical best practices through informal technical leadership, design reviews, and knowledge sharing

Contribute to IP development, publications, and external technical engagements as appropriate

Qualifications

PhD or equivalent industry experience in Electrical Engineering, Physics, Materials Science, or Device Engineering

Approximately 15–25 years of professional R&D experience in semiconductor device development

Deep expertise in GaN or other wide-bandgap semiconductors (e.g., SiC), with a strong preference for power device experience

Demonstrated track record of technical impact and innovation in advanced device development programs

Required Technical Skills & Experience

Extensive experience with power device design in GaN and/or SiC, including vertical device concepts

In-depth understanding of semiconductor manufacturing processes, integration challenges, and yield considerations

Proven experience working in shared fab and foundry environments, including external technology transfers

Strong proficiency in TCAD simulation for device physics, scaling, and optimization

Advanced data analysis skills using Python, MATLAB, or equivalent tools

Hands-on experience with GDS layout and test structure design

Expertise in wide-bandgap power device failure analysis and reliability physics

Experience with on-wafer automated DC/CV/dynamic testing and discrete component characterization