Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.

Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.

The Opportunity

Quadric is building the world’s first General-Purpose Neural Processing Unit (GPNPU) architecture, bringing high-performance AI, DSP, and ML compute to edge devices. As a Deep Learning Compiler Engineer, you will design and optimize the compiler stack (MLIR, TVM, LLVM) that bridges state-of-the-art neural network frameworks directly to our proprietary hardware architecture. You'll play a critical role in unlocking peak hardware performance, low latency, and memory efficiency for edge AI workloads.

What You'll Do

Deep Learning Compiler Infrastructure & Optimization

Design, implement, and maintain compiler optimization passes targeting Quadric’s processor architecture using frameworks like MLIR, Apache TVM, or LLVM.

Develop lowering pathways from high-level machine learning frameworks (PyTorch, TensorFlow, ONNX) down to optimized low-level kernel code.

Optimize neural network performance for memory throughput, latency, compute unit utilization, and power consumption.

Neural Network Model Parsing & Graph Transformation

Implement graph-level optimizations, including operator fusion, layout transformation, quantization (INT8/FP16), and memory allocation strategies.

Analyze novel deep learning model topologies (Transformers, CNNs, Vision-Language Models) and extend compiler support for new operators and primitives.

Benchmark and profile end-to-end model performance to identify and resolve compiler bottlenecks.

Hardware-Software Co-Design

Collaborate closely with hardware and micro-architecture teams to define instruction set extensions, hardware acceleration features, and compiler requirements.

Develop software simulators, functional models, and test benches to validate compiler correctness and generated binary performance.

Participate in hardware bring-up and validation efforts on FPGA and ASIC platforms.

What Success Looks Like

Within your first 6–12 months, you'll

Successfully integrate support for key deep learning models (e.g., modern Transformer architectures or Vision models) into Quadric's compiler pipeline.

Implement custom graph and codegen optimization passes that deliver measurable performance improvements on target benchmarks.

Partner with the architecture team to influence the next-generation micro-architecture definition through data-driven workload analysis.

What We're Looking For

Required

BS, MS, or Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field.

8+ years Hands-on experience developing deep learning compilers or compiler infrastructures (e.g., MLIR, Apache TVM, LLVM, XLA, TensorRT, or Glow).

Strong proficiency in C++ (14/17/20) and Python, with solid fundamentals in data structures, algorithms, and object-oriented design.

Familiarity with modern AI/ML frameworks (PyTorch, TensorFlow, ONNX) and deep learning operator representations.

Solid understanding of computer systems, memory hierarchies, parallel processing, and CPU/GPU/NPU instruction execution.

Preferred

Experience with low-level kernel optimization, SIMD/vector programming, and memory allocation strategy development.

Knowledge of model quantization methodologies (INT8, FP8, mixed-precision) and post-training/QAT optimization techniques.

Prior experience working on software stacks for custom AI accelerators, DSPs, or embedded architectures.