About Architect Labs

Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.

What You’ll Do

As a Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of the on-chip interconnect fabric and high-speed I/O data movement subsystems going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for NoC routers, crossbar switches, high-speed fabric bridges, and peer-to-peer data transfer engines — ensuring low-latency, high-bandwidth, and deadlock-free communication across all SoC agents.

Core Responsibilities

Own the on-chip fabric RTL end-to-end: from NoC topology and router microarchitecture through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.

Design and implement AMBA-based interconnect fabrics: including AXI/ACE/CHI-compliant crossbar switches, network interfaces (NIs), protocol converters (AXI-to-CHI bridges, AXI-to-AHB/APB downconverters), and multi-layer interconnect configurations optimized for ML accelerator traffic patterns.

Architect NoC routers and topologies: including virtual-channel routers, wormhole/flit-based switching, adaptive routing algorithms, QoS-aware arbitration (bandwidth regulation, latency-critical path prioritization), and deadlock-free network design for mesh/ring/tree topologies.

Design high-speed I/O fabric bridges and peer-to-peer engines: including PCIe/CXL-to-fabric bridges, chip-to-chip interconnect logic (UCIe, custom die-to-die links), peer-to-peer DMA controllers for direct device-to-device transfers bypassing host memory, and coherent/non-coherent multi-chip fabric extensions.

Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (latency vs. bandwidth vs. area, coherence overhead vs. performance), and feed area/timing/power realities back into the architecture and internal AI systems.

Define and maintain interface specifications: AMBA AXI4/AXI5, ACE/ACE-Lite, CHI (with snoop filter interfaces), AXI-Stream for streaming datapaths, custom sideband channels for QoS/ordering, and high-speed SerDes-facing interfaces for off-chip links.

Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, NoC configuration generators, regression flows, lint/CDC waivers, and integration collateral for the interconnect subsystem.

Close collaboration with DV: Support verification bring-up with interconnect reference models, protocol compliance checkers (AXI/CHI protocol monitors), SVA assertions for ordering rules and deadlock freedom, coverage plans targeting corner-case traffic scenarios (multi-master contention, QoS starvation), and architectural documentation for verification closure.

Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your interconnect domain expertise — particularly around traffic modeling and fabric configuration optimization.

Support FPGA prototyping on Xilinx for early functional validation of the fabric, including multi-master traffic generation and performance characterization on FPGA platforms.

What We’d Like to See

Required Qualifications

Degree: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.

Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.