Join our hardware team as an intern or co-op verifying the CPU core and cache hierarchy, with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.

What you'll do

Work with your mentor to develop verification plans for the CPU core and cache hierarchy
Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
Build tests, scoreboards, and reference models, and close functional and code coverage
Triage and root-cause failures with RTL designers, with mentorship from senior engineers
Participate in design and verification reviews and document your verification environment and results

Requirements

Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
Familiarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory
Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
Understanding of the end-to-end ASIC design flow and general VLSI concepts
Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus