The Verification Engineer will define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals. He/She will also be responsible for the simulations of the SOC

Responsibilities

Define overall verification strategies, methodologies, and simulation environment
Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.
Develop, maintain and publish verification specifications.
Analyze and debug simulation failures
Generates code coverage and functional coverage report
Run gate level simulation and debug them.
Perform the constraint assertion-based verification

Qualifications and Skills

BS in EE with 3+ years of experience or MS in EE with 1+ year experience
Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
Fluent in verification language such as UVM/OVM/System Verilog, Vera, Verilog
Experience in writing Test-plans and creating directed and random test cases
Strong scripting skills in Perl, Python, Linux shells etc.