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NUVACORE

CPU Physical Design (RTL to GDS)

Austin, TX; Santa Clara, CAHybrid · United States
Full Time · ENGINEERING
POSTED 8 SEPTVERIFIED 11H AGO
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Role
62 days opentrue age
Posted 8 Sept
Payats field
$140k–250kposted
▲ +5% vs market median $185k
$140k$250k
Market p25–p75
$140k–$212k
NUVACORE p25–p75
$195kn=11
H-1B median · Software engineering
$183k
Austin · n=123 · 365d to 6 Nov
CompanyNUVACORE →
20open roles
Opened · 30d
+0
Closed · 30d
−1
7d of snapshots · 30d window
Market
37,653open · Software engineering
Opened · 7d
+2,3546% of open
All software engineering
75,188open
All tracked boards · live 10 Nov · n=37,653
Visa
7H-1B LCAs · FY26
Median wage
$183k
LCAs FY26 · n=7 · to 2026-06-26

At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. As a member of CPU - specific custom circuit design team, you will enable the design to achieve the target PPA Specifications for the product.

THE ROLE

As a CPU Physical Design (PD) Engineer, you will participate in the following :

Responsible for evaluating RTL and micro-Architecture designs, providing feasibility assessments and actionable feedback.

Responsible for driving end-to-end design closure from RTL to GDS/Tape-out, ensuring target PPAS (Power, Performance, Area & Schedule) commitments are met.

Responsible for coordinating and aligning with CAD, RTL/µ-arch, and other partner teams to ensure seamless execution throughout the design cycle.

Responsible for leading and influencing the definition and adoption of Tools, Flows, and Methodology (TFM) to drive design efficiency and establish team-wide best practices

MUST TO HAVE

Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.

Proficient in industry-standard EDA tools with experience applied to CPU design workflows.

Demonstrated track record of successfully delivering production-level designs through tape-out.

Proven experience in PPA optimization across CPU units and design blocks.

Deep understanding of end-to-end physical design closure, spanning all signoff domains

Well-versed in timing constraints for both Functional and DFT (Design for Test) modes.

Strong communication and collaboration skills

REQUIREMENTS — NICE TO HAVE

Source · NUVACOREFirst seen 2 NovOriginal ↗