About SK hynix America

At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.

Work Model: Onsite

Job Overview:

SK hynix America is seeking a highly experienced and motivated ADK (Assembly Design Kit) engineer to join our Advanced Packaging R&D team. In this critical role, you will be at the forefront of semiconductor innovation, leading the development of robust design rules and verification flows for our next-generation 2.5D/3D Interposer and Heterogeneous Integration technologies.

You will serve as the vital bridge between package architecture, process integration, and design implementation. Your primary responsibility will be defining the Design Rules, DRC (Design Rule Check), and LVS (Layout vs. Schematic) frameworks that ensure our advanced designs are manufactural, reliable, and high-yielding. The ideal candidate possesses deep expertise in Physical Verification (PV), a comprehensive understanding of semiconductor packaging processes (specifically TSV, Micro-bump, bridge die and RDL), and the strategic ability to translate complex process constraints into design rules. Furthermore, you will play a key role in optimizing the overall design-to-signoff flow, ensuring seamless integration across multidisciplinary teams.

Responsibilities

ADK Development & Maintenance: Lead the creation and maintenance of comprehensive Assembly Design Kits (ADK) tailored for advanced packaging technologies (2.5D/3D IC, SiP, Fan-Out).
Rule Definition & Verification: Define, debug, and validate Design Rules (DRC) and Layout vs. Schematic (LVS) checks, accounting for package-specific constraints such as bump placement, RDL routing, TSV integration, and wire bonding.
Cross-Functional Collaboration: Partner closely with package design, process integration, and manufacturing teams to ensure design rule accuracy, maximize yield, and accelerate time-to-market.
Physical Verification Support: Provide expert support to design teams in resolving complex physical verification issues arising from die-to-package integration and heterogeneous stacking.
Flow Automation & Optimization: Develop and automate verification flows using advanced scripting, integrating tools from Synopsys, Cadence, and Siemens EDA to enhance efficiency and data integrity.
Design Flow Strategy: Analyze and optimize the end-to-end package design flow, identifying bottlenecks and implementing best practices to streamline the journey from concept to GDSII sign-off.

Qualifications

Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
Experience: Minimum 3+ years of hands-on experience in Physical Design, CAD, or PDK/ADK development within the semiconductor or packaging industry.
Tool Proficiency: Extensive experience with industry-standard sign-off tools from multiple vendors such as Synopsys (IC Validator, 3DICC), Cadence (PVS, Virtuoso, Integrity 3D-IC), Siemens EDA (Calibre)
Technical Skills: Deep knowledge of design rule structures, verification methodologies, and GDSII/OASIS data formats.

Preferred Qualifications:

Design Flow Expertise: Proven track record in managing physical design flows from concept to GDSII/OASIS sign-off. Ability to translate process constraints into design rules, whether in advanced packaging or front-end logic/foundry technologies.
Scripting skills: Proficiency in Tcl, Perl, Python, or SKILL for flow automation is highly preferred.