About SK hynix America

At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.

Work Model: Onsite

Job Summary

SK hynix America is seeking a skilled and motivated Signal‑Integrity and Power‑Integrity (SIPI) Engineer to join our Advanced Packaging (PKG) R&D team. In this role, you will be at the forefront of semiconductor innovation, driving the analysis, and validation of advanced System-in-Package (SiP) solutions for next-generation memory technologies, including High-Bandwidth Memory (HBM), interposer-based architectures, and GPU-integrated systems. This role focuses exclusively on 2.5D/3D packaging innovations, driving electrical integrity and power delivery robustness for cutting-edge semiconductor platforms. The position requires deep technical understanding in high-speed interface design, collaboration with global R&D teams, and contributions to industry standards for advanced memory packaging.

Job Responsibilities

Strategic Roadmap Execution: Define and drive the SIPI roadmap for advanced packaging families, ensuring technical strategies align with product specifications and business objectives.
Architecture & Design Leadership: Lead the development of high-performance SiP architectures (HBM, interposer, 3D stacks) and validate power delivery and signal integrity across the full stack—from silicon to substrate.
Methodology Development & Implementation: Establish and deploy best-practice SIPI methodologies, including electromagnetic extraction, multi-port S-parameter modeling, and power-network analysis tailored for complex 2.5D/3D environments.
Cross-Functional Collaboration: Partner closely with circuit designers, layout teams, process integration, yield engineering, and system architects to ensure seamless translation of design specifications into manufacturable packages.
Knowledge Sharing & Team Growth: Act as a technical resource for junior and peer engineers, fostering expertise in SIPI analysis and design verification while championing knowledge exchange across global teams.

Qualifications and Education Requirements

Master’s degree or higher in Electrical Engineering, or a related field. Candidates with relevant industry experience are preferred
Experience: ≥ 5 years of experience in SIPI analysis in advanced semiconductor packaging.
Technical Expertise: Proven knowledge of 2.5 D/3 D package architectures, HBM, interposer, TSV, high‑speed I/O standards, and power‑delivery networks.
Simulation Tools: Proven proficiency with SIPI simulation tools (e.g., Synopsys 3DICC, Cadence Integrity 3D-IC/Sigrity, Ansys AEDT(Q3D, HFSS)/Siwave/RedHawk, HSPICE, Keysight ADS).
Analytical Skills: Ability to interpret complex simulation data and translate it into actionable engineering recommendations.
Communication: Excellent verbal and written communication skills; ability to present complex technical concepts to both engineering and executive audiences.

Preferred Skills

Currently pursuing a PhD's degree in Electrical Engineering or a related field
Hands-on experience with 2.5D/3D packaging for HBM, interposers, or GPU-memory integration.
Expertise in power integrity (PI) for 3D-stacked memory systems, including PDN impedance profiling and IBIS model validation for HBM.
In‑depth familiarity with industry standards such as PCIe Gen5/Gen6, CXL, UCIe, and JEDEC memory specifications.
Proficiency in scripting/automation (Python, TCL, SKILL) to create custom analysis flows and improve productivity.