Staff HSIO Digital & Mixed Signal Design Engineer
Please Note:
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
Please Note
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
Please Note
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
Samsung’s San Jose Location Group in US was established in October 2012 to develop industry leading location technology IP for mobile and wearable applications. The group develops premium tier products and drives the technology for next generation products. The team is responsible for all aspects of building products from concept (algorithm design) to productization – i.e., architecture definition, silicon design, algorithm and software development, platform integration, performance optimization, test and commercialization. The Location Group is an integral part of the broader SoC organization responsible for Exynos line of SoC products that cover all IPs including Application Processor, Communication Processor, Connectivity, GPU, NPU etc. and hence enables us to develop highly integrated products and optimize our solution to be the best in class.
This team is focused on next-generation HSIO (High-Speed I/O) design for Samsung’s AI production platforms. Ideal candidates will have 3+ years of industry experience specializing in digital design for die-to-die(chiplet) interfaces or similar high-speed I/O technologies.
Candidates are expected to have a strong understanding of the end-to-end digital design flow and the ability to collaborate effectively with system and analog teams.
Location: Working onsite at our San Jose headquarters
What You’ll Do
- BS in Electrical Engineering with 10+ years of experience or MS in Electrical Engineering with 8+ years of experience or PhD in Electrical Engineering with 5+ years of experience
- Hands-on experience with HSIO PHY IP (e.g., UCIe, BOW, PCIe), including:
- Deep understanding of high-speed serial interconnect protocols and associated design trade-offs