SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the team

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The hardware design team writes the RTL for SambaNova's RDU, the processor behind our AI workload acceleration systems, covering the compute, memory, and networking subsystems. Engineers own specific blocks inside a larger subsystem, working alongside the principal engineers and architects who set its direction. A block stays with the engineer who wrote it through PPA closure, tapeout, and bring-up, so you debug your own design in silicon.

About the role

SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work alongside principal engineers, architects, design verification engineers, and physical design engineers to implement innovative features in hardware that provide unique value to SambaNova.

In this role you will take ownership of blocks within a larger subsystem — contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tapeout, and silicon bring-up. You will grow your scope over time as you build depth in our architecture.

This role is onsite, based in either our San Jose, CA or Austin, TX office.

Responsibilities

Some of your responsibilities will include...

Work with principal engineers and architects to author sections of the microarchitecture specification for compute, memory, or networking subsystems.
Code, integrate, and debug SystemVerilog RTL for assigned blocks through the chip implementation and production lifecycle.
Meet Power, Performance, and Area (PPA) targets for your blocks using advanced digital design techniques for high-speed design.
Partner with design verification and physical design engineers to converge on functionality, timing, and area.
Implement SystemVerilog Assertions (SVA) and run lint, CDC, and LEC flows to check design intent and keep blocks clean.
Participate in design reviews, presenting your design decisions and incorporating feedback.
Support post-silicon bring-up and debug for the blocks you own.
Contribute to design flow improvements, including AI and automation in EDA tool methodologies.

Required qualifications

Master's degree in Computer Engineering or Electrical Engineering with 3–5 years of relevant experience, or Bachelor's degree with 5–7 years.
Solid foundation in computer architecture and digital logic design.
Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs.
Experience making design decisions that trade off Power, Performance, and Area (PPA).
Working knowledge of industry-standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).
Experience with digital logic synthesis tools and Static Timing Analysis (STA).
Proficiency with industry-standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).