About the Role

We are seeking a Product Engineer / Product Operations Engineer to serve as the critical link between design, test, manufacturing, and the customer, and to help stand up the product-engineering / product-operations function from the ground up. In this role you will own products from first silicon through qualification, ramp, and sustaining—driving yield, test quality, cost, and supply to ensure our multi-die devices ship on time, at the volumes datacenter silicon demands, and at target margin. You will partner with DFT, design, and test engineering, and help establish the foundry/OSAT and operations relationships needed to take products from bring-up through ramp and sustaining for advanced-packaging datacenter silicon.

What you'll do

Own assigned products across the full lifecycle: new product introduction (NPI), characterization, qualification, ramp, and sustaining

Drive yield analysis and improvement—monitor wafer sort and final test yield, lead failure analysis and root-cause efforts, and partner with design/test to close gaps

Own the multi-die yield story—known-good-die (KGD) sorting, die-matching and binning across a package, assembly and packaging yield, and cost-per-package risk (a single marginal die can sink an entire multi-die assembly)

Manage test program quality and optimization across wafer sort, final test, and system-level test (SLT)—test time reduction, coverage vs. cost trade-offs, guardbands, and outlier/screening strategies (PAT/SBL/SYL) used to screen marginal die for KGD

Lead silicon characterization across PVT corners; define spec limits, shmoo analysis, and datasheet correlation

Own product qualification (HTOL, HAST, TC, ESD/latch-up, etc.) and reliability sign-off in line with JEDEC standards as applicable

Establish and drive production operations: lot dispositioning, capacity and WIP management, binning/grading strategy, and coordination with foundry and OSAT (assembly/test) partners

Monitor and act on production data—SPC, yield dashboards, and statistical analysis (JMP/Python) to detect excursions and drive corrective action

Lead excursion management and 8D/CAPA—contain, root-cause, and resolve manufacturing and quality issues; establish customer-return (RMA/FA) handling

Drive cost reduction and continuous improvement—test time, yield, package, and material cost initiatives

Help establish customer-quality processes—field issue resolution, quality reporting, and audits

What we're looking for

Bachelor's or Master's in Electrical Engineering, Materials/Semiconductor Engineering, or related field

Hands-on experience in semiconductor product engineering, test engineering, or operations for complex digital/SoC/ASIC products

Strong understanding of the semiconductor manufacturing flow—wafer fab, wafer sort, assembly, and final test

Multi-die / advanced-package product engineering—known-good-die (KGD) sorting, die-to-package matching and binning, assembly and packaging yield, and cost-per-package management

Experience with foundry and OSAT relationships and offshore test/assembly operations

Experience with ATE platforms (Advantest, Teradyne) and test program development, debug, and optimization, including system-level test (SLT)

Solid grounding in yield analysis, statistics, and data analysis—SPC, distributions, correlation; proficiency with JMP, Python, or equivalent

Experience with silicon characterization (PVT corners, shmoo, spec setting) and datasheet correlation

Working knowledge of product qualification and reliability methodologies (JEDEC).

Familiarity with DFT/test concepts—scan, MBIST, ATPG patterns, boundary scan—and how they map to production test

Knowledge of outlier screening methods (PAT/SBL/SYL) applied to known-good-die (KGD) screening—identifying marginal die before they are committed to an expensive multi-die package

Experience with NPI program management and product ramp/sustaining for advanced-packaging datacenter silicon

Familiarity with multi-die package technologies and assembly processes.

Structured problem-solving / continuous-improvement methodology (8D, CAPA, DOE, or equivalent)