Senior ASIC Design Engineer

Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems. Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.

Duties & Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.

• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.

• Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.

• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.

• Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.

• Optimize designs for performance, power, and area (PPA).

• Perform RTL simulation and debugging to ensure design functionality and performance.

• Contribute to block-level and top-level integration, verification, and silicon bring-up.

• Participate in architecture and design reviews and provide technical guidance to other engineers.

• Collaborate with cross-functional teams to troubleshoot complex design and system-level issues.

• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.

• Contribute to ASIC development from architecture and RTL through tapeout and silicon validation.

Required Qualifications

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.

• 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.

• Strong proficiency in Verilog and/or SystemVerilog.

• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.

• Hands-on experience with ASIC design flows and industry-standard EDA tools.

• Strong knowledge of one or more of the following areas

- Digital Signal Processing (DSP)

- High-speed SerDes

- Analog/Mixed-Signal ICs

- Digital communications

- Optical communications

• Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.

• Understanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.

• Experience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.

• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.

• Familiarity with verification methodologies such as UVM and/or formal verification.

• Knowledge of low-power design techniques and PPA optimization.

• Strong analytical and problem-solving skills.

• Excellent communication and teamwork skills with the ability to work effectively in a fast-paced startup environment.

Preferred Qualifications

• Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.

• Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.

• Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.

• Experience working with advanced semiconductor process technologies.

• Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.