About the Role

Join a hardware team developing a new class of computing chips based on thermodynamic computing. You will design circuits across analog, mixed-signal, and probabilistic domains, helping take new chip architectures from concept through silicon.

What You'll Do

Design analog and mixed-signal circuit blocks, including ADCs, PLLs, band gaps, regulators, oscillators, high-speed dividers, and SerDes.

Own block-level design across multiple chips, from architecture and schematic development through layout and tape-out verification, including DRC, ERC, and LVS.

Perform hands-on layout and Cadence simulations, including parasitic extraction, Monte Carlo, and corner analysis.

Support lab testing and validation with signal generators, spectrum analyzers, and oscilloscopes.

Collaborate with IC, systems, physics, and algorithms teams to bring sampling circuits from concept to silicon.

What We're Looking For

Three to six years of CMOS analog and mixed-signal IC design experience, with an MS or PhD in Electrical Engineering focused on analog or mixed-signal design.

Multiple tape-outs, ideally using FinFET or 28 nm or 65 nm processes.

Experience designing one or more of ADCs, PLLs, oscillators, regulators, or high-speed SerDes, along with exposure to a range of circuit types.

Mixed-signal design experience, hands-on layout skills, and proficiency with Cadence. Python and C/C++ are relevant tools.

Ability to perform small-signal and feedback analysis, including closed-loop gain, loading effects, and Miller analysis.

A practical, hands-on approach and willingness to work across circuit areas beyond your primary specialty.

Compensation & Benefits

Base salary range: $160,000 to $300,000 annually. Visa sponsorship is available.

Location

Hybrid, with three days per week on-site in Boston, Massachusetts, United States.