About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX. Full-time onsite position.

Reports To: Chief Scientist

FLSA Status: Exempt

Position Overview

We are seeking a hands-on Nanofabrication and Characterization Engineer to build and characterize prototype metasurface chips for our optical vector-matrix multiplication (OVMM) engine. Prototypes made in university cleanrooms let us try new metasurface designs, materials, and process changes in weeks rather than waiting on a full foundry cycle. This role owns that fast path: you will turn electromagnetic designs into masks and process flows, fabricate multilevel metal–dielectric nanostructures, integrate the active tunable layer and package the device, and measure what you built so every run teaches us something.

You will spend most of your time in shared-user university nanofabrication facilities and in our own lab: running lithography, deposition, etch, and planarization steps, inspecting and cross-sectioning devices, and measuring their optical and electro-optic response. The rest of your time goes to process documentation, run tracking, and data analysis. If you combine strong cleanroom process skills with the drive to test your own devices, this role will let you own the metasurface prototyping line, from design to measured device.

Key Responsibilities

Process Flow Development: Turn metasurface designs into complete, multi-step process flows and travelers. Select lithography, deposition, etch, and planarization steps that meet target dimensions and tolerances with the tools at hand.

Nanoscale Lithography: Pattern sub-200 nm features and align multiple layers using electron-beam lithography and optical or deep-UV steppers. Develop and maintain dose, proximity-correction, and resist recipes.

Thin-Film Deposition and Etch: Deposit and etch metals, dielectrics, and thin conformal liners (sputtering, evaporation, PECVD, ALD, RIE/ICP). Control thickness, sidewall profile, and aspect ratio to nanometer-level tolerances.

Multilevel Integration: Build stacked metal–dielectric structures with vias and planarization (CMP, damascene, or lift-off). Diagnose and fix yield problems that arise between layers: misalignment, dishing, voids, and adhesion.

Active Layer and Device Assembly: Integrate the electro-optically tunable material layer, including surface preparation, alignment and encapsulation layers, cell assembly, and sealing. Dice, mount, and wire-bond devices for testing.

Process Metrology: Inspect every run with SEM, FIB cross-sections, AFM, profilometry, and ellipsometry. Feed measured dimensions back into the design so it models the as-built device.

Optical and Electro-Optic Characterization: Measure the reflectance, spectra, polarization response, and voltage-dependent tuning of finished devices on microscope-based optical benches. Compare results against simulation and trace gaps to specific design or process causes.