About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX or Sunnyvale, CA. Full-time onsite position.

Reports To: Director of Silicon Photonics

FLSA Status: Exempt

Position Overview

Neurophos is looking for a Silicon Photonics Engineer to lead the receiver (Rx) photonic integrated circuit for our OPU platform, including the T100 optical AI inference chip. You will own the Rx PIC from photodetector device design through chip-level architecture: how light reaches the chip, how it is coupled and routed, and how large photodetector arrays convert it into clean, high-speed electrical signals for the TIAs. You will take designs through tapeout and silicon validation. Working closely with the electronic IC, optics, and packaging teams, you will balance bandwidth, sensitivity, noise, density, and power at the system level.

Key Responsibilities

Define the Rx PIC architecture, including optical input coupling (free-space and waveguide), routing, demultiplexing where needed, and the layout of dense photodetector arrays, all against system-level link and power budgets.

Design and optimize high-speed photodetectors (e.g., Ge-on-Si PIN and avalanche, waveguide-coupled and surface-normal) for responsivity, dark current, capacitance, bandwidth, linearity, and saturation.

Model the device and receiver with optical, electrical, and RF simulation (e.g., Lumerical FDTD/CHARGE/INTERCONNECT, HFSS, TCAD), including photodetector equivalent circuits for co-design with the TIA.

Work with the electronic IC team on the PD–TIA interface (pad and interconnect parasitics, bias, input-referred noise, sensitivity), including flip-chip, 3D, and co-packaged integration.

Analyze array-level effects such as optical and electrical crosstalk, uniformity, thermal behavior, and yield, and define test structures and design-for-test features to measure them.

Lead layout, verification, and tapeout of Rx PIC test vehicles and product blocks in foundry silicon photonics PDKs.

Support die- and wafer-level characterization with the test team (responsivity, dark current, O/E bandwidth, sensitivity, BER), and use the measurements to calibrate models and improve the next design.

Evaluate new detector materials, structures, and coupling approaches that could improve receiver performance or density beyond what the current platform supports.

Qualifications

PhD in a relevant field, such as Electrical Engineering, Applied Physics, or Physics.

3 years of relevant experience in high-speed silicon photonics, focused on photodetectors and receiver PICs.

Hands-on design experience with Ge-on-Si (or equivalent) high-speed photodetectors, including the trade-offs among responsivity, bandwidth, capacitance, and dark current.

Proficiency with photonic and device simulation tools (e.g., Lumerical/Ansys, COMSOL, Synopsys TCAD, or equivalent) and with circuit-level modeling of photodetectors.