What MatX Is Building

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

What You'll Do Here

Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design

Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design

Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout

Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results

Who You Are

Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon

5+ years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows

Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities

Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals

Hands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to take designs to high quality sign-off

Experience on DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and area for designs working with experts in these areas to take designs to sign-off

Familiarity with verification, emulation platforms and methodologies is a plus

Hands-on experience with participation in silicon debug and bring-up is a plus

This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday

Bonus Points If You Have

A huge plus if you have hands-on experience with silicon and firmware implementations of PCIe, HBM, DMA, Die-to-die subsystems.

Compensation

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job-related skills, and relevant education and training. Career length is only a guideline for compensation.

Early Career - $160,000 - $275,000 + equity

Mid Career - $175,000 - $400,000 + equity

Senior Career - $250,000 - $600,000 + equity

What We Offer

Time off: 4 weeks PTO (accrued) + 12 company Holidays + up to 3 weeks remote work

Health: Company-subsidized Medical (Kaiser or Anthem) for employees & dependents, Guardian Dental and Vision insurances for employee & dependents, and life insurance (employee only), plus HSA and FSA offerings via Lively.

Financial Security: Choose from Roth or pre-tax 401K (or both) with a 5% company contribution (even if you don't contribute), 100% company-paid life insurance (up to $300K), long-term disability and travel insurance.

Professional Development: $1500 per year Professional Development Budget

Team Meals: MatX provides onsite team lunch & dinner Monday - Friday, with your choice of ordering via WeBox, Specialty’s or via our reimbursement system

Commute on Us: We pay 100% for your daily commute. Commute via our company rideshare account, reimburse public transportation, or get a Fasttrak card (or all three)