ABOUT LUMILENS

At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing - faster, cooler, and massively more efficient.

We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. At Lumilens, we’re developing high-speed photonics products purpose-built to power the future of AI infrastructure and high-performance computing.

This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in scaling optical systems. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.

If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.

About the Role

Lumilens is revolutionizing AI compute infrastructure with next-generation photonic interconnects, enabling massive scale-out and scale-up architectures through co-packaged optics (CPO), near-packaged optics (NPO), high-density silicon photonics, and advanced heterogeneous integration.

We're looking for a world-class Senior / Principal Power Integrity Engineer to own and drive power delivery strategies across complex 2.5D/3D packages that integrate electrical ICs, photonic ICs, chiplets, and high-bandwidth memory. You'll architect robust, low-noise, high-efficiency PDNs that support extreme power densities, tight voltage margins, and ultra-high-speed signaling—critical for powering the world's largest AI clusters without compromising performance or reliability.

Key Responsibilities

Define and implement power integrity architectures for 2.5D/3D heterogeneous integration, including chiplet-based designs, interposer/substrate scaling, on-package voltage regulation, multi-rail PDN topologies, decoupling strategies, and power-aware thermal co-design.

Perform comprehensive full-stack power integrity analysis and optimization—from die-level IR drop and electromigration to package-level PDN impedance profiling, transient response, and system-level power delivery network (PDN) validation.

Model, simulate, and validate power delivery solutions using industry-leading tools (e.g., Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, or equivalent) across silicon, interposer, substrate, and board interfaces.

Lead power integrity co-design with silicon design, package engineering, and photonics teams to optimize bump maps, power/ground grid layouts, TSV/RDL routing, on-die decoupling, and voltage regulator placement for minimal noise, IR drop, and EMI in CPO/NPO systems.

Drive selection and qualification of advanced power components (VRMs, capacitors, inductors, low-loss substrates, advanced TIMs) and collaborate with foundry/OSAT partners on PDN process capabilities, manufacturability, yield, and cost.

Develop and refine power integrity methodologies, design rules, and sign-off criteria tailored to high-performance AI accelerators, photonic transceivers, and chiplet architectures.

Analyze and mitigate power-related reliability risks, including electromigration, thermal-induced voltage droop, power sequencing, and long-term stability under dynamic AI workloads.

Partner with cross-functional teams (architecture, Si design, package design, system engineering, supply chain) to explore emerging technologies, influence roadmaps, generate proof-of-concepts, and protect IP that maximizes power efficiency and performance.

Own power integrity qualification, lab validation (using high-bandwidth scopes, VNAs, spectrum analyzers), correlation to simulation, and readiness for volume production ramp.

Required Qualifications

Deep expertise in power integrity for high-performance semiconductors, with strong knowledge of PDN design principles, frequency-domain analysis, transient response, on-chip/off-chip decoupling, IR drop/EM analysis, and noise mitigation techniques.