The Opportunity

Lumai is moving from optical-compute research into production AI systems, and the architecture and compiler decisions that shape the product are being made now, ahead of the silicon that will confirm them. This hire builds the modelling capability those decisions rest on.

The Role

You will own the performance and power modelling framework that predicts how Lumai's photonic AI hardware performs against real inference workloads, giving the architecture and compiler teams one shared source of truth for latency, throughput and power across device configurations. You will model the compute engines, interconnect, memory and bridge interfaces; keep the model honest by characterising operator-level workloads against hardware, RTL or emulation results; and turn what the model says into decisions teams act on.

What is genuinely hard about this is balancing speed, fidelity and usability. The model has to capture concurrency, event-driven behaviour and compute-block latency in enough detail to support real architecture decisions, and still compare configurations in minutes rather than overnight. The gap between what the model predicts and what the hardware does has to be measured rather than assumed, and closing it is the part that never stops.

By month six, you will have a reliable modelling flow for priority workloads and device configurations, a demonstrated path for closing the gap between model and hardware, and a simulator the architecture and compiler teams use to make decisions rather than a side artefact. You will report to the Head of Architecture or the VP of Engineering, and may build a small team around the capability.

What You'll Do

Design, build and maintain a Python-based framework that models hardware and software latency, hardware concurrency and event-driven relationships.

Model compute engines, interconnect and synchronisation fabric, memory and bridge interfaces, and accelerator blocks across device configurations.

Characterise convolution, depthwise convolution, pooling, attention and other operator workloads against hardware, RTL or emulation results.

Build compiler-agnostic interfaces that ingest compiled models and MLIR from multiple internal compiler flows.

Analyse simulation traces with the architecture and compiler teams to improve layer-to-hardware mappings and resolve performance discrepancies.

Run industry benchmarks and representative models - UL Procyon, Geekbench AI, Stable Diffusion and contemporary LLMs - to produce decision-ready KPIs.

Develop block-level power models and validate worst-case power scenarios with the micro-architecture, verification and physical-design teams.

Own the CI/CD pipelines and simulation flows that keep results reliable and reproducible as usage scales.

Translate modelling findings into architecture and compiler decisions, setting technical direction and developing engineers or interns as the team grows.

What We're Looking For

Must-have

Proven experience building or substantially extending a hardware/software performance modelling or simulation framework for AI/ML accelerators, ideally in Python.

Strong understanding of hardware concurrency, event-driven modelling and AI inference accelerator micro-architecture: compute, memory hierarchy, interconnect and dataflow.

Hands-on experience characterising AI operators and correlating model predictions with real hardware or hardware-accurate reference data.

Familiarity with compiler internals and intermediate representations such as MLIR, including tooling that consumes compiler output to drive simulation.

Strong software engineering and technical leadership practice: framework design, CI/CD ownership, and direction or review of junior engineers' or interns' work.

Strong preference for

Direct experience with NPU, GPU or other edge or client AI inference accelerator architectures.

Experience across multiple compiler toolchains, reconciling architecture-level and production compiler behaviour.

Exposure to power modelling, RTL, emulation, FPGA prototyping, photonic compute or another non-traditional compute architecture.