Kandou is a semiconductor company pioneering high-performance interconnect and chip-to-chip communication solutions. Our engineering teams push the boundaries of what is possible in silicon design, validation, and system integration. We are looking for a seasoned Silicon Validation Lead to join our R&D organization and drive end-to-end validation of complex SoC platforms.

Silicon Validation Manager

Location: Hyderabad

Department: Silicon Engineering / Hardware Validation

Employment Type: Full-Time

Role Overview

As the Silicon Validation Director/Manager, you will own the full lifecycle of silicon bring-up and validation for next-generation SoC platforms that integrate PCIe, CXL, DDR5, RISC-V processors, Memory Fabric, PCIe Switch, and Caliptra Root of Trust (RoT) subsystems. You will lead a cross-functional validation team, define test strategies, and act as the primary technical interface between design, architecture, firmware, and system teams to ensure first-pass silicon quality and robust production readiness.

Key Responsibilities

Silicon Bring-Up & Validation

Lead pre- and post-silicon validation for complex SoCs encompassing PCIe Gen 4/5/6, CXL 1.1/2.0/3.0, DDR5 memory subsystems, RISC-V processor cores, Memory Fabric, PCIe Switch, and Caliptra RoT IP.

Drive silicon bring-up from power-on through full functional validation, characterization, and compliance testing.

Develop and own comprehensive silicon validation plans, test coverage matrices, and sign-off criteria aligned with tapeout and production milestones.

Execute and manage compliance and interoperability testing against PCIe, CXL, JEDEC DDR5, and relevant security/RoT standards.

Test Architecture & Strategy

Define test infrastructure architecture: board-level bring-up environments, FPGA prototypes, simulation correlation, and lab automation frameworks.

Drive development of validation collateral including test plans, test suites, regression frameworks, and pass/fail criteria for all integrated subsystems.

Establish coverage tracking dashboards and triage processes to systematically reduce validation escapes.

Debug & Root Cause Analysis

Lead deep-dive debugging of complex multi-layer failures spanning RTL, firmware, hardware, and system software.

Utilize protocol analyzers, logic analyzers, oscilloscopes, and CXL/PCIe test equipment (e.g., Teledyne LeCroy, Keysight, Spirent) to isolate and characterize issues.

Author and maintain detailed bug reports, failure analysis documents, and errata for silicon revisions.

Team Leadership & Collaboration

Lead and mentor a team of validation engineers; set technical direction, review deliverables, and foster a culture of engineering rigor.

Collaborate closely with RTL design, DV, firmware, and software teams to ensure seamless hand-off from pre-silicon simulation to physical silicon validation.

Interface with external IP vendors, OEM/ODM partners, and compliance labs for interoperability and certification activities.

Represent the validation team in architecture reviews, design reviews, and program planning meetings.

Process & Continuous Improvement

Champion test automation and CI/CD integration for regression management.

Drive lessons-learned processes across silicon spins and contribute to validation methodology improvements.

Establish and maintain lab safety, equipment inventory, and test asset management best practices.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

18+ years of hands-on silicon validation or hardware validation engineering experience, with at least 6 years in a Manager/Lead or staff-level role.

Deep expertise in PCIe (Gen 4/5/6): protocol-level knowledge, compliance testing, physical layer characterization, and debug.

Strong hands-on experience with CXL (1.1 / 2.0 / 3.0): memory semantic protocols, device types (Type 1/2/3), coherency mechanisms, and interoperability testing.

Extensive experience validating DDR5 memory subsystems: timing margins, signal integrity, JEDEC compliance, and RAS features.