At Kandou, we are redeﬁning the economics of AI infrastructure. Our mission is to democratise AI by signiﬁcantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption signiﬁcantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Job Title: Digital Verification Engineer

Location: Hyderabad OR Bangalore

Key Responsibilities

Develop design verification methodologies and implement standard debug flows

Work with designers in verification and validation of circuit designs

Participate in design reviews

Prepare design verification plan based on design specifications

Plan and schedule assigned projects for timely completion

Utilize the latest techniques, tools, and technologies for design verification activities

Maintain design verification environment and track & close design bugs

Skills

Must possess great communication skills, rigorous with an analytical mind and be a strong team player

Good scripting techniques, regression setup & management

Deep understanding of simulation and verification environments

Strong knowledge on Metrics-driven verification (incl. test planning and coverage closure)

Deep knowledge of simulations tools and debugging techniques

Understanding of verification planning and test bench development using the latest methodologies

Experience with 3rd party VIP usage and test development (a big plus)

Experience with Assertion Based Verification (a big plus)

Experience

5+ years’ experience in the semiconductor industry

Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC

Skilled in trade-offs between quality and schedule

Experience in constrained random test bench development

Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous

Extensive digital verification background with some UVM experience

Education

Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !

Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/