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Etched

Silicon Validation Engineer, Software

San JoseOnsite · United States
FullTime · ASIC
POSTED 3 SEPTVERIFIED 25M AGO
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Pay · Etched
$250k–$275k
p25–p75 · n=32
Open for
61d
since 3 Sept
H-1B · FY26
5
certified LCAs
Hiring · 30d
121
−2 net · open roles
PythonC++

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a skilled and motivated Silicon Validation Firmware Engineer to develop the firmware and low-level software that validates our AI/ML accelerator ASICs across their entire Lifecycle, from pre-silicon emulation and FPGA prototyping through post-silicon bring-up, characterization, and production ramp. In this role you will build the validation firmware, test content, and automation that prove our silicon works, and you will be hands-on debugging real hardware in the lab. Your work directly enables functional correctness, performance, and reliability of our cutting-edge products.

Key Responsibilities

Develop and own low-level validation firmware in C/C++ that runs across emulation and physical silicon, providing test content pre-silicon and reusing it to drive post-silicon bring-up.

Drive early bring-up of first silicon: boot, initialization, feature enablement, and debug of ASICs.

Perform deep-dive debug of silicon issues spanning firmware, RTL, electrical, protocol, and system levels; root-cause and resolve failures.

Build firmware infrastructure including hardware abstraction layers (HALs) and low-level device drivers for compute units, memory subsystems, and high-speed interfaces.

Develop and extend validation automation, result-capture, and regression frameworks (CI/CD) to run validation at scale.

Author firmware-driven test plans and define coverage metrics across IP blocks and subsystems; execute functional, performance, and stress/corner-case testing.

Validate and characterize custom IP blocks and accelerator components on both pre- and post-silicon platforms.

Use debug consoles and lab tooling (JTAG, UART, logic/protocol analyzers) for silicon debug and characterization.

Collaborate closely with design, verification, architecture, DFT, and driver teams to ensure a smooth transition from pre-silicon verification to post-silicon validation, and to feed silicon issues back into revisions and firmware/driver workarounds.

You may be a good fit if you have (Must-have qualifications)

Proficiency in C/C++ for firmware and bare-metal development, plus Python for validation automation and scripting.

Understanding of SoC/computer architecture (CPU cores, memory subsystems, caches, interconnects).

Solid low-level/embedded fundamentals: bootloaders, hardware abstraction layers, device drivers, register/interrupt programming, and bare-metal or RTOS environments.

Knowledge and familiarity developing and debugging in Linux environments.

Strong problem-solving, analytical, and cross-functional collaboration skills across hardware and software teams.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (Master's a plus).

Strong candidates may also have experience with (Nice-to-have qualifications)

2+ years of experience developing firmware / embedded software for ASICs or SoCs

Hands-on experience with silicon bring-up and low-level debug (boot, initialization, root-causing failures across firmware/electrical/protocol layers).

Experience with JTAG and debuggers (e.g., Lauterbach/GDB) and serial/UART debug consoles.

Experience across both pre-silicon (emulation, FPGA, RTL simulation) and post-silicon (lab bring-up, characterization) environments.

Experience with one or more high-speed interfaces: PCIe, DDR/LPDDR/HBM, SerDes, or die-to-die / chiplet interconnect.

Experience building test/validation automation and regression frameworks (CI/CD).

RTOS experience (FreeRTOS, Zephyr, NuttX) or RISC-V firmware development.

Familiarity with platform/system firmware (UEFI, ACPI, BMC, BIOS).

Source · EtchedFirst seen 2 NovOriginal ↗